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843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 1 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary g eneral d escription the ics843034-01 is a general purpose, low phase noise lvpecl synthesizer which can generate frequencies for a wide variety of applications. the ics843034-01 has a 4:1 input multiplexer from which the following inputs can be selected: 1 differential input, 1 single-ended input, or one of two crystal oscillators, thus making the device ideal for frequency translation or generation. each differential lvpecl output pair has an output divider which can be independently set so that two different frequencies can be generated. additionally, each lvpecl output pair has a dedicated power supply pin so the outputs can run at 3.3v or 2.5v. the ics843034-01 also supplies a buffered copy of the reference clock or crystal frequency on the single-ended ref_clk pin which can be enabled or disabled (disabled by default). the output frequency can be programmed using either a serial or parallel programming interface. the ics843034-01 has excellent <1ps phase jitter performance over the 637khz - 5mhz integration range, thus making it suitable for use in fibre channel, sonet, and ethernet/1gb ethernet applications. example applications include systems which must support both fec and non fec rates. in 10gb fibre channel, for example, you can use a 25.5mhz crystal to generate a 159.375mhz reference clock, and then switch to a 20.544mhz crystal to generate 164.355mhz for 66/64 fec. other applications could include supporting both ethernet frequencies and sonet frequencies in an application. when ethernet frequencies are needed, a 25mhz crystal can be used and when sonet frequencies are needed, the input mux can be switched to select a 38.88mhz crystal. f eatures ? dual differential 3.3v lvpecl outputs which can be set independently for either 3.3v or 2.5v ? 4:1 input mux: 1 differential input 1 single-ended input 2 crystal oscillator interfaces ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? test_clk accepts lvcmos or lvttl input levels ? output frequency range: 30.625mhz to 640mhz ? crystal input frequency range: 12mhz to 40mhz ? vco range: 490mhz to 640mhz ? parallel or serial interface for programming feedback divider and output dividers ? rms phase jitter at 106.25mhz, using a 25.5mhz crystal (637khz to 5mhz): 0.61ps (typical) ? supply voltage modes: lvpecl outputs (core/outputs): 3.3v/3.3v 3.3v/2.5v ref_clk output (core/outputs): 3.3v/3.3v 3.3v/2.5v ? 0c to 70c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages hiperclocks? ic s p in a ssignment 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 m8 nb0 nb1 nb2 oe_ref oe_a oe_b v cc na0 na1 na2 v ee xtal_out1 xtal_in1 xtal_out0 xtal_in0 test_clk sel1 sel0 v cca s_load s_data s_clock mr clk nclk np_load vco_sel m0 m1 m2 m3 m4 m5 m6 m7 ics843034-01 48-pin lqfp 7mm x 7mm x 1.4mm package body y package top view v ee p_div v cco _ ref ref_clk v cco _ b nfoutb0 foutb0 v cco _ a nfouta0 fouta0 v cc test the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 2 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary osc c i l m 0 0 1 001 0 1 1 1 01 11 1 16 000 1 001 2 0 1 0 3 0 1 1 4 5 1 01 6 8 111 16 osc p ha se d ete c t o r v co 00 01 1 0 11 1 4 0 8 fouta0 nfouta0 foutb0 nfoutb0 ref_clk test v cco_ref v cco_a v cco_b oe_a vco_sel xtal_in0 xtal_out0 xtal_in1 xtal_out1 clk nclk test_clk sel1 sel0 p_div oe_b mr oe_ref s_load s_data s_clock np_load m8:m0 na2:na0 nb2:nb0 b lock d iagram
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 3 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary nx bits can be hardwired to set the m divider and nx output divider to a specific default state that will automatically occur during power-up. the test output is low when operating in the parallel input mode. the relationship between the vco fre- quency, the crystal frequency and the m divider is defined as follows: the m value and the required values of m0 through m5 are shown in table 3b to program the vco frequency function table. valid m values for which the pll will achieve lock for a 25mhz reference are defined as 20 m 25. the frequency out is de- fined as follows: serial operation occurs when np_load is high and s_load is low. the shift register is loaded by sampling the s_data bits with the rising edge of s_clock. the contents of the shift register are loaded into the m divider and nx output di- vider when s_load transitions from low-to-high. the m divide and nx output divide values are latched on the high- to-low transition of s_load. if s_load is held high, data at the s_data input is passed directly to the m divider and nx output divider on each rising edge of s_clock. the serial mode can be used to program the m and nx bits and test bits t1 and t0. the internal registers t0 and t1 determine the state of the test output as follows: f unctional d escription note: the functional description that follows describes op- eration using a 25mhz crystal. valid pll loop divider values for different crystal or input frequencies are defined in the in- put frequency characteristics, table 5, note 1. the ics843034-01 features a fully integrated pll and there- fore requires no external components for setting the loop band- width. a fundamental crystal is used as the input to the on- chip oscillator. the output of the oscillator is fed into the phase detector. a 25mhz crystal provides a 25mhz phase detector reference frequency. the vco of the pll operates over a range of 490mhz to 640mhz. the output of the m divider is also applied to the phase detector. the phase detector and the m divider force the vco output fre- quency to be m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low), the pll will not achieve lock. the output of the vco is scaled by a divider prior to being sent to each of the lvpecl output buffers. the divider provides a 50% output duty cycle. the ics843034-01 supports either serial or parallel program- ming modes to program the m feedback divider and n output divider. the input divider p can only be changed using the p_div pin. it cannot be changed from the default 1 setting using the serial interface. figure 1 shows the timing diagram for each mode. in parallel mode, the np_load input is initially low. the data on the m, na, and nb inputs are passed directly to the m di- vider and both n output dividers. on the low-to-high transi- tion of the np_load input, the data is latched and the m and n dividers remain loaded until the next low transition on np_load or until a serial event occurs. as a result, the m and t1 t0 test output 0 0 low 0 1 s_data, shift register output 1 0 output of m divider 1 1 cmos fout a0 f igure 1. p arallel & s erial l oad o perations t 1 t0 nb2 nb1 nb0 na2 na1 na0 m8 m7 m6 m5 m4 m3 m2 m1 m0 s_clock s_data s_load np_load m0:m8, p_div, na0:na2, nb0:nb2 np_load fvco = fxtal x m p fout = fvco = fxtal x m nn x p s erial l oading p arallel l oading m, n, p t s t s t h t s t h time s_load
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 4 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 18 mt u p n in w o d l l u p d a o l _ p n f o n o i t i s n r t h g i h - o t - w o l n o d e h c t a l a t a d . t u p n i r e d i v i d m . s l e v e l c a f r e t n i l t t v l / s o m c v l . t u p n i 3 , 21 b n , 0 b nt u p n ip u l l u p , c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f 42 b nt u p n in w o d l l u p 5f e r _ e ot u p n in w o d l l u p . t u p t u o k l c _ f e r f o g n i l b a s i d d n a g n i l b a n e s l o r t n o c . e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 6a _ e ot u p n ip u l l u p , 0 a t u o f f o g n i l b a s i d d n a g n i l b a n e s l o r t n o c . e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o 0 a t u o f n 7b _ e ot u p n ip u l l u p , 0 b t u o f f o g n i l b a s i d d n a g n i l b a n e s l o r t n o c . e l b a n e t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p t u o 0 b t u o f n 4 1 , 8v c c r e w o p. s n i p y l p p u s e r o c 0 1 , 91 a n , 0 a nt u p n ip u l l u p , c 3 e l b a t n i d e n i f e d s a e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f 1 12 a nt u p n in w o d l l u p 4 2 , 2 1v e e r e w o p. s n i p y l p p u s e v i t a g e n 3 1t s e tt u p t u o . n o i t a r e p o f o e d o m l a i r e s e h t n i e v i t c a s i h c i h w t u p t u o t s e t . e d o m l e l l a r a p n i w o l n e v i r d t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 6 1 , 5 1 , 0 a t u o f 0 a t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 7 1v a _ o c c r e w o p. 0 a t u o f n , 0 a t u o f r o f n i p y l p p u s t u p t u o 9 1 , 8 1 , 0 b t u o f 0 b t u o f n t u p t u o . s l e v e l e c a f r e t n i l c e p v l . r e z i s e h t n y s e h t r o f t u p t u o l a i t n e r e f f i d 0 2v b _ o c c r e w o p. 0 b t u o f n , 0 b t u o f r o f n i p y l p p u s t u p t u o 1 2k l c _ f e rt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e c n e r e f e r 2 2v f e r _ o c c r e w o p. k l c _ f e r r o f n i p y l p p u s t u p t u o 3 2v i d _ pt u p n i / p u l l u p n w o d l l u p = 1 , ) t l u a f e d ( 1 = t a o l f . t c e l e s e d i v i d t u p n i . 8 = 0 , 4 . s l e v e l e c a f r e t n i l t t v l / s o m c v l 5 2r mt u p n in w o d l l u p l a n r e t n i e h t s e c r o f , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a e h t d n a w o l o g o t x t u o f s t u p t u o e u r t e h t g n i s u a c t e s e r e r a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t x t u o f n s t u p t u o d e t r e v n i t o n s e o d r m f o n o i t r e s s a . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s e u l a v t d n a , n , m d e d a o l t c e f f a 6 2k c o l c _ st u p n in w o d l l u p r e t s i g e r t f i h s e h t o t n i t u p n i a t a d _ s t a t n e s e r p a t a d l a i r e s n i s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o e g d e g n i s i r e h t n o 7 2a t a d _ st u p n in w o d l l u p e g d e g n i s i r e h t n o d e l p m a s a t a d . t u p n i l a i r e s r e t s i g e r t f i h s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . k c o l c _ s f o 8 2d a o l _ st u p n in w o d l l u p . s r e d i v i d e h t o t n i r e t s i g e r t f i h s m o r f a t a d f o n o i t i s n a r t s l o r t n o c . s l e v e l e c a f r e t n i l t t v l / s o m c v l 9 2v a c c r e w o p. n i p y l p p u s g o l a n a 1 3 , 0 31 l e s , 0 l e st u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i t c e l e s k c o l c 2 3k l c _ t s e tt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c t s e t 4 3 , 3 3 , 0 n i _ l a t x 0 t u o _ l a t x t u p n i. e c a f r e t n i r o t a l l i c s o l a t s y r c 6 3 , 5 3 , 1 n i _ l a t x 1 t u o _ l a t x t u p n i. e c a f r e t n i r o t a l l i c s o l a t s y r c 7 3k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 8 3k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / . . . e g a p t x e n n o d e u n i t n o c
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 5 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u o 57 2 1 r e b m u ne m a ne p y tn o i t p i r c s e d 9 3d a o l _ p nt u p n in w o d l l u p s i 0 m : 5 m t a t n e s e r p a t a d n e h w s e n i m r e t e d . t u p n i d a o l l e l l a r a p d n a 0 a n : 2 a n t a t n e s e r p a t a d n e h w d n a , r e d i v i d m o t n i d e d a o l . s r e d i v i d t u p t u o n e h t o t n i d e d a o l s i 0 b n : 2 b n . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 4l e s _ o c vt u p n ip u l l u p . e d o m s s a p y b r o l l p n i s i r e z i s e h t n y s r e h t e h w s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 3 4 , 2 4 , 1 4 8 4 , 7 4 , 5 4 , 4 4 , 2 m , 1 m , 0 m 7 m , 6 m , 4 m , 3 m t u p n in w o d l l u p n o i t i s n a r t h g i h - o t - w o l n o d e h c t a l a t a d . s t u p n i r e d i v i d m . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i d a o l _ p n f o 6 45 mt u p n ip u l l u p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 6 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 3a. p arallel and s erial m ode f unction t able s t u p n i s n o i t i d n o c r md a o l _ p nmnd a o l _ sk c o l c _ sa t a d _ s hx xxx x x . w o l s t u p t u o s e c r o f . t e s e r ll a t a da t a dx x x m e h t o t y l t c e r i d d e s s a p s t u p n i n d n a m n o a t a d . w o l d e c r o f t u p t u o t s e t . r e d i v i d t u p t u o n d n a r e d i v i d l a t a da t a dl x x d e d a o l s n i a m e r d n a s r e t s i g e r t u p n i o t n i d e h c t a l s i a t a d . s r u c c o t n e v e l a i r e s a l i t n u r o n o i t i s n a r t w o l t x e n l i t n u lh xxl a t a d n o a t a d h t i w d e d a o l s i r e t s i g e r t f i h s . e d o m t u p n i l a i r e s . k c o l c _ s f o e g d e g n i s i r h c a e n o a t a d _ s lh xx la t a d e h t o t d e s s a p e r a r e t s i g e r t f i h s e h t f o s t n e t n o c . r e d i v i d t u p t u o n d n a r e d i v i d m lh xx la t a d. d e h c t a l e r a s e u l a v r e d i v i d t u p t u o n d n a r e d i v i d m lh xxl x x . s r e t s i g e r t f i h s t c e f f a t o n o d t u p n i l a i r e s r o l e l l a r a p lh xxh a t a d. d e k c o l c s i t i s a r e d i v i d m o t y l t c e r i d d e s s a p a t a d _ s w o l = l : e t o n h g i h = h e r a c t ' n o d = x n o i t i s n a r t e g d e g n i s i r = n o i t i s n a r t e g d e g n i l l a f = t able 3b. p rogrammable vco f requency f unction t able p = 1 (p_div = f loat ) t able 3c. p rogrammable o utput d ivider f unction t able y c n e u q e r f o c v ) z h m ( e d i v i d m 2 36 18421 5 m4 m3 m2 m1 m0 m 0 0 50 2 0 10 10 0 ? ? ?????? 0 5 52 2010110 ? ? ?????? 5 2 65 2 0 1100 1 r o l a t s y r c o t d n o p s e r r o c s e i c n e u q e r f g n i t l u s e r e h t d n a s e u l a v e d i v i d m e s e h t : 1 e t o n . z h m 5 2 f o y c n e u q e r f t u p n i k l c _ t s e t s t u p n i e u l a v r e d i v i d n ) z h m ( y c n e u q e r f t u p t u o 2 x n *1 x n *0 x n *m u m i n i mm u m i x a m 00 0 1 0 9 40 4 6 00 1 2 5 4 20 2 3 010 3 3 3 . 3 6 13 3 . 3 1 2 011 4 5 . 2 2 10 6 1 10 0 5 8 98 2 1 10 1 6 7 6 . 1 87 6 . 6 0 1 110 8 5 2 . 1 60 8 11 1 6 15 2 6 . 0 30 4 b k n a b r o a k n a b s e t o n e d x : e t o n *
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 7 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 4a. p ower s upply dc c haracteristics , v cc = v cca = 3.3v5%, v cco_a = v cco_b = 3.3v5% or 2.5v5%, t a = 0c to 70c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cco + 0.5v outputs, i o (lvpecl) continuous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 7 3 . 23 . 35 6 4 . 3v v a c c e g a t l o v y l p p u s g o l a n a 5 7 3 . 23 . 35 6 4 . 3v v , a _ o c c v b _ o c c y l p p u s t u p t u o e g a t l o v 5 3 1 . 33 . 35 6 4 . 3v 5 7 3 . 25 . 25 2 6 . 2v i e e t n e r r u c y l p p u s r e w o p 5 8 1a m i a c c t n e r r u c y l p p u s g o l a n a 0 2a m v f e r _ o c c y l p p u s t u p t u o k l c _ f e r 5 3 1 . 33 . 35 6 4 . 3v 5 7 3 . 25 . 25 2 6 . 2v
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 8 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 4b. lvcmos/lvttl dc c haracteristics , v cc = v cca = 3.3v5%, v cco_a = v cco_b = 3.3v5% or 2.5v5%, t a = 0c to 70c) note 1: output terminated with 50 to v cco_ref /2. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c nv n i v = c c v 5 6 4 . 3 =0 5 1a k l cv n i v = c c v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv n i v , v 0 = c c v 5 6 4 . 3 =0 5 1 -a k l cv n i v , v 0 = c c v 5 6 4 . 3 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n , v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t c c . v 3 . 0 + s i e g a t l o v e d o m n o m m o c : 2 e t o nv s a d e n i f e d h i . t able 4c. d ifferential dc c haracteristics , v cc = v cca = 3.3v5%, v cco_a = v cco_b = 3.3v5% or 2.5v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h , r m , 1 l e s , 0 l e s , l e s _ o c v , b _ e o , a _ e o , f e r _ e o , a t a d _ s , d a o l _ p n , d a o l _ s , k l c _ t s e t , k c o l c _ s 2 x n : 0 x n , 5 m : 0 m 2v c c 3 . 0 +v v i d _ pv c c 4 . 0 -v v l i t u p n i e g a t l o v w o l , r m , 1 l e s , 0 l e s , l e s _ o c v , b _ e o , a _ e o , f e r _ e o , a t a d _ s , d a o l _ p n , d a o l _ s , k l c _ t s e t , k c o l c _ s 2 x n : 0 x n , 5 m : 0 m 3 . 0 -8 . 0v v i d _ p 3 . 0v i h i t u p n i t n e r r u c h g i h , r m , v i d _ p , k l c _ t s e t , a t a d _ s , k c o l c _ s , ] 0 : 1 [ l e s f e r _ e o , d a o l _ p n , d a o l _ s 8 m : 6 m , 4 m : 1 m , 2 b n , 2 a n v c c v = n i v 5 6 4 . 3 =0 5 1a , 5 m , 1 a n , 0 a n , 1 b n , 0 b n l e s _ o c v , b _ e o , a _ e o v c c v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , r m , v i d _ p , k l c _ t s e t , a t a d _ s , k c o l c _ s , ] 0 : 1 [ l e s f e r _ e o , d a o l _ p n , d a o l _ s 8 m : 6 m , 4 m : 1 m , 2 b n , 2 a n v c c , v 5 6 4 . 3 = v n i v 0 = 5 -a , 5 m , 1 a n , 0 a n , 1 b n , 0 b n l e s _ o c v , b _ e o , a _ e o v c c , v 5 6 4 . 3 = v n i v 0 = 0 5 1 -a v h o t u p t u o e g a t l o v h g i h 1 e t o n ; t s e t v o c c % 5 v 3 . 3 =6 . 2v v o c c % 5 v 5 . 2 =8 . 1v v l o w o l t u p t u o e g a t l o v 1 e t o n ; t s e t v o c c , % 5 v 3 . 3 = v o c c % 5 v 5 . 2 = 5 . 0v
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 9 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 5. i nput f requency c haracteristics , v cc = v cca = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i t u p n i y c n e u q e r f 0 t u o _ l a t x , 0 n i _ l a t x2 10 4z h m 1 t u o _ l a t x , 1 n i _ l a t x2 10 4z h m k c o l c _ s 0 5z h m t r t / f e m i t e s i rd a o l _ s , a t a d _ s , k c o l c _ s 6s n e t a r e p o o t o c v e h t r o f t e s e b t s u m e u l a v m e h t , e g n a r y c n e u q e r f k l c _ t s e t d n a k l c n / k l c , l a t s y r c t u p n i e h t r o f : e t o n 1 4 e r a m f o s e u l a v d i l a v , z h m 2 1 f o y c n e u q e r f t u p n i m u m i n i m e h t g n i s u . e g n a r z h m 0 4 6 o t z h m 0 9 4 e h t n i h t i w m 3 5 . = p r e d i v i d t u p n i h t i w 3 1 e r a m f o s e u l a v d i l a v , z h m 0 4 f o y c n e u q e r f m u m i x a m e h t g n i s u . ) 0 0 = v i d _ p ( 1 m . 6 1 t able 6. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 2 10 4z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 5 2 6 . 0 30 4 6z h m t ) ? ( t i j ; ) m o d n a r ( s m r , r e t t i j e s a h p 1 e t o n : e g n a r n o i t a r g e t n i z h m 5 - z h k 7 3 6 1 6 . 0s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o e m a s e h t @ d e r u s a e m y c n e u q e r f t u p t u o 0 5s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p t s e m i t p u t e s d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n t h e m i t d l o h d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n c d oe l c y c y t u d t u p t u o 0 5% t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n t able 7a. ac c haracteristics , v cc = v cca = v cco_a = v cco_b = 3.3v5%, t a = 0c to 70c t able 4d. lvpecl dc c haracteristics , v cco_a = v cco_b = 2.375v to 3.465v, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u ov o c c 4 . 1 -v o c c 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u ov o c c 0 . 2 -v o c c 7 . 1 -v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t x _ o c c . v 2 -
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 10 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 7b. ac c haracteristics , v cc = v cca = 3.3v5%, v cco_a = v cco_b = 2.5v5%, t a = 0c to 70c t able 7c. ac c haracteristics , v cc = v cca = 3.3v5%, v cco_a = 3.3v5%, v cco_b = 2.5v5%,t a = 0c to 70c or v cc = v cca = 3.3v5%, v cco_a = 2.5v5%, v cco_b = 3.3v5%,t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 5 30 0 7z h m t ) ? ( t i j ; ) m o d n a r ( s m r , r e t t i j e s a h p 1 e t o n : e g n a r n o i t a r g e t n i z h m 5 - z h k 7 3 6 1 7 . 0s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 0 5s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p t s e m i t p u t e s d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n t h e m i t d l o h d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n c d oe l c y c y t u d t u p t u o 0 5% t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 5 2 6 . 0 30 4 6z h m t ) ? ( t i j ; ) m o d n a r ( s m r , r e t t i j e s a h p 1 e t o n : e g n a r n o i t a r g e t n i z h m 5 - z h k 7 3 6 1 7 . 0s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 0 5s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 7s p t s e m i t p u t e s d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n t h e m i t d l o h d a o l _ p n o t n , m5s n k c o l c _ s o t a t a d _ s5s n d a o l _ s o t k c o l c _ s5s n c d oe l c y c y t u d t u p t u o 0 5% t k c o l e m i t k c o l l l p 1s m . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 11 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t ypical p hase n oise at 106.25mh z 106.25mhz rms phase jitter (random) 637khz to 5mhz = 0.61ps (typical) 0 -10 -20 -30 - 40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m o ffset f requency (h z ) n oise p ower dbc hz phase noise result by adding a filter to raw data raw phase noise data filter ? ? ?
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 12 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary v oh v ref v ol mean period (first edge after trigger) reference point (trigger edge) 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10 -7 )% of all measurements histogram t sk(o) nfoutx foutx nfouty fouty p arameter m easurement i nformation 3.3v c ore /2.5v ref_clk o utput l oad ac t est c ircuit 3.3v c ore /3.3v o utput l oad ac t est c ircuit fouta0/nfouta0, foutb0/nfoutb0 scope qx nqx lvpecl 2v -1.3v 0.165v v cc , v cca , v cco_a, v cco_b v ee 3.3vc ore /3.3v ref_clk o utput l oad ac t est c ircuit 3.3v c ore /2.5v o utput l oad ac t est c ircuit fouta0/nfouta0, foutb0/nfoutb0 scope qx nqx lvpecl 2.8v0.04v -0.5v 0.125v v cc , v cca v ee v cco_a, v cco_b 2v scope qx lvcmos 1.65v5% -1.65v 5% v ee o utput s kew p eriod j itter scope qx lvcmos 2.05v0.04v -1.25v 5% 1.25v5% v ee v cc , v cca , v cco_ref v cc , v cca v cco_ref
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 13 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary o utput d uty c ycle /o utput p ulse w idth /p eriod o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% fouta0 nfouta0
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 14 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics843034-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc , v cca , and v cco_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 2 illustrates how a 24 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. p ower s upply f iltering t echniques f igure 2. p ower s upply f iltering 24 v cca 10 f .01 f 3.3v .01 f v cc a pplication i nformation figure 3 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded lvcmos/lvttl l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc f igure 3. s ingle e nded s ignal d riving d ifferential i nput
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 15 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary figure 4. c rystal i npu t i nterface ics84332 c rystal i nput i nterface the ics843034-01 has been characterized with 18pf paral- lel resonant crystals. the capacitor values, c1 and c2, shown in figure 4 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. ics843034-01 c1 22p x1 18pf parallel crystal c2 22p xtal_out xtal_in f igure 5c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 5b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 5d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5d show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 5a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 5a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 16 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. foutx and nfoutx are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminat- ing resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 6b. lvpecl o utput t ermination f igure 6a. lvpecl o utput t ermination drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 6a and 6b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utput i nputs : c rystal i nput : for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. clk i nput : for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left floating. we recommend that there is no trace attached. lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 17 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t ermination for 2.5v lvpecl o utput figure 7a and figure 7b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to ter- minating 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 7b can be eliminated and the termination is shown in figure 7c. f igure 7c. 2.5v lvpecl t ermination e xample r2 50 zo = 50 ohm vcco=2.5v r1 50 zo = 50 ohm + - 2.5v 2,5v lvpecl driv er f igure 7b. 2.5v lvpecl d river t ermination e xample vcco=2.5v r1 50 r2 50 zo = 50 ohm r3 18 2,5v lvpecl driv er zo = 50 ohm + - 2.5v f igure 7a. 2.5v lvpecl d river t ermination e xample r2 62.5 2.5v 2,5v lvpecl driv er r3 250 zo = 50 ohm zo = 50 ohm r4 62.5 2.5v + - r1 250 vcco=2.5v
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 18 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics843034-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843034-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 185ma = 641mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power _max (3.465v, with all outputs switching) = 641mw + 60mw = 701mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 8 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.701w * 42.1c/w = 99.5c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) t able 8. t hermal r esistance ja for 48- pin lqfp, f orced c onvection 0 200 500 single-layer pcb, jedec standard test boards 67. 8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47. 9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 19 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 8. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 8. lvpecl d river c ircuit and t ermination q1 v out v cco rl 50 v cco - 2v
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 20 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ics843034-01 is: 5084 t able 9. ja vs . a ir f low t able for 48 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 21 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary p ackage o utline - y s uffix for 48 l ead lqfp t able 10. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c b b m u m i n i ml a n i m o nm u m i x a m n 8 4 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 5 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 5 . 5 e c i s a b 0 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -8 0 . 0
843034ay-01 www.icst.com/products/hiperclocks.html rev. c november 28, 2005 22 integrated circuit systems, inc. ics843034-01 f emto c locks ? m ulti -r at e lvpecl f requency s ynthesizer preliminary t able 11. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks? and f emto c locks ? is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - y a 4 3 0 3 4 8 s c i1 0 a 4 3 0 3 4 8 s c ip f q l d a e l 8 4y a r tc 0 7 o t c 0 t 1 0 - y a 4 3 0 3 4 8 s c i1 0 a 4 3 0 3 4 8 s c ip f q l d a e l 8 4l e e r & e p a t 0 0 0 1c 0 7 o t c 0 f l 1 0 - y a 4 3 0 3 4 8 s c il 1 0 a 4 3 0 3 4 s c ip f q l " e e r f - d a e l " d a e l 8 4y a r tc 0 7 o t c 0 t f l 1 0 - y a 4 3 0 3 4 8 s c il 1 0 a 4 3 0 3 4 s c ip f q l " e e r f - d a e l " d a e l 8 4l e e r & e p a t 0 0 0 1c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r d r o e r a t a h t s t r a p : e t o n

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